1. Field of the Invention
The present invention relates generally to overload current response in a power supply output, and relates more particularly to a system and method for responding to an overload current in a power supply output FET using a class D topology approach.
2. Description of Related Art
Overload conditions in power switches are a concern for robust operation of power devices, such as power supplies or power controllers. Overcurrent conditions can lead to component damage, alter component characteristics or cause system failures, for example. Accordingly, a fast and appropriate response to current overload conditions is highly desirable in a control applied to a power switch.
FIGS. 1-3 illustrate conventional power supply control circuits for supplying power to a load. Typically, a switch, referred to herein variously as a power switch or a pass FET 15, is switched on and off to supply backplane supply power to a load 17. A capacitor Cgate is coupled to the gate of pass FET 15 to contribute to maintaining a gate voltage for enhanced operation of pass FET 15. A current sense resistor Rsense is used to sense output load current, and can indicate when an overload condition exists. In typical operation, a slew current Islew is provided to the gate of pass FET 15 to turn pass FET 15 on slowly to avoid a voltage droop or spike on the backplane power supply that can impact other power supply systems. In the case of the conventional circuit illustrated in FIG. 3, the slew current is provided by a linear op-amp 33, which is also used to respond to overcurrent conditions.
One conventional response to overload conditions in a power switch is to rapidly shut down the power switch, typically leading to a power shut down in the load coupled to the power switch. Referring to FIG. 1, a circuit for a conventional approach to controlling a power switch in the presence of a current overload is illustrated generally as circuit 10. Circuit 10 includes flip-flop 12 that acts as a latch, and overload comparator 13, that together provide a latching comparator overload response. Comparator 13 is a fast comparator that can be used to rapidly shut down pass FET 15. When pass FET 15 is rapidly shut down, power is removed from the load. Due to the latch characteristics of flip-flop 12, pass FET 15 is maintained in an off state after detection of a current overload condition.
Referring to FIG. 2, a circuit for responding to a current overload condition is illustrated generally as circuit 20. Circuit 20 includes a retry timer 24 that permits a retry response upon detection of a current overload. Circuit 20 provides a fast shut down, similar to circuit 10, and then attempts a control retry to operate pass FET 15. The fast shut down provided in circuits 10 and 20 both provide a rapid power removal from the load to render the load circuits completely off when a current overload condition is detected. The fast current overload shutdown response can also be triggered in the presence of a transient, such as may occur in switching circuits, or in the presence of noise. For example, load circuitry may include a microprocessor that can cause power spikes during turn on, or a capacitive load that can spike the power supply. Retry timer 24 may not be able to handle power spikes with differing characteristics, or may cause a power oscillation when system noise causes the current overload detector to trip.
Referring now to FIG. 3, a circuit 30 is shown for another approach to provide a response to a current overload condition. Circuit 30 includes linear op-amp 33 that acts as a controlled current limiter. Op-amp 33 contributes to controlling current provided to the load, but has a slow response time, which may result in excessive current flow. When an overcurrent condition occurs, op-amp 33 may not be able to respond in time to prevent damage or destruction to pass FET 15. Another drawback of the design of circuit 30 is that the slow response time of op-amp 33 may permit excessive current to flow causing a drop in the backplane voltage supply. In addition, linear op-amp 33 uses a large chip area to obtain a high band width circuit that has a low impedance gate drive. It can also be difficult to construct linear op-amp 33 to have stable operation over a wide range of control parameters.
It would be desirable to obtain a design for response to an overload current condition that is rapid and simple, without a large circuit size.